Such an arrangement may include:
a low pass filter; PA1 an oscillator, whose output is an output of said arrangement; PA1 a subtracter to a positive input of which a binary signal is applied and an output of which is coupled to a negative input thereof via the series coupling of said filter and said oscillator; PA1 a gapped clock generating a gapped clock stream normally constituted by consecutive like patterns each comprising pulses and gaps; PA1 a control signal generator means providing at least a control signal; PA1 a control means which in response to said control signal controls said gapped clock by adapting said patterns of said gapped clock stream; PA1 a counter means which under the control of said controlled gapped clock stream provides said binary signal. PA1 a second subtracter having a second positive input coupled to the output of said first subtracter, a second negative input, and a second output coupled to said low pass filter; PA1 a second clock; and PA1 a correction means controlled by said control signal and by said second clock and providing at its output, which is coupled to said second negative input, a correction value which is varied to zero at the rate of said second clock and which is varied with a predetermined value under the control of said control signal. PA1 a second correction circuit providing a second correction value which is zero except when indicated by a second control signal in which case it is equal to a second predetermined constant; and PA1 a summator with a first positive input coupled to the output of said second subtracter, with an output coupled to said low pass filter input, and with a second positive input connected to an output of said second correction circuit. PA1 a buffer memory to an input of which said bitstream is applied, said write address constituting said binary signal input to said phase locked loop arrangement, and said output of said phase locked loop arrangement providing a read address for said buffer memory.
Such a digital phase locked loop arrangement is already known in the art, e.g. from the article `Design and performance verification of a SONET-to-DS3 desynchronizer` by R. W. Hamlin, published in Globecom '91, 22.7.1-22.7.4, pp. 761-764. FIG. 1 of this article shows signals STS-1 and DS3 which are both digital signals having distinct frame structures each comprising an overhead part with control bits and a payload part with information bits. The signal DS3 is mapped in the payload part of the signal STS-1. The above phase locked loop arrangement is used in connection with a FIFO (First In First Out) buffer to remove jitter from the payload part of the DS3 signal as extracted from the STS-1 signal. This jitter is due to so-called overhead gapping, i.e. overhead--in the STS-1 and DS3 frame structures--which is not extracted from the STS-1 signal to obtain the payload part of the DS3 signal. The bits of the DS3 signal are written into the FIFO buffer at write addresses which constitute the binary input signal applied to the phase locked loop arrangements. As already mentioned, the write address is provided by the counter means controlled by the gapped clock. The latter clock forms part of the block `pointer averaging circuit` shown in FIG. 3 of the above article and is derived under the control of the control means also included in the latter block, from a gapped DS3 clock which in its turn is derived in the block `pointer tracking and DS3 destuff` shown in FIG. 2 of the above article, from the regular STS-1 clock by replacing pulses thereof with gaps when bits of the corresponding DS3 signal do not carry information but overhead.
The gapped DS3 clock and therefore also the gapped clock derived from it and used in the phase locked loop arrangement account for so-called bit stuffings and pointer movements. Bit stuffing occurs when a specific overhead bit of the DS3 signal contains information and is indicated by stuff control bits (constituting the above control signal) included in the overhead of the DS3 signal. To be noted that bit stuffing may occur when a so-called plesiochronous signal is mapped in the payload part of the DS3 signal, because of absence of synchronism between the plesiochronous and DS3 signals. A pointer movement may occur because of the mapping of the DS3 signal in the STS-1 signal. Indeed, to allow such mapping the STS-1 overhead contains a pointer value which in the STS-1 payload points to the beginning of the DS3 frame. Due to absence of synchronism of the DS3 and STS-1 signals, the beginning of the DS3 frame in the STS-1 payload and hence the pointer value, may vary from STS-1 frame to STS-1 frame. This is referred to as a pointer movement and the control signal for this pointer movement is constituted by the so-called H1 and H2 bytes included in the overhead of the STS-1 signal. In case of such a pointer movement, either the so-called H3 byte which is also part of the STS-1 overhead contains DS3 data (DS3 overhead or payload) or the byte which follows the H3 bytes and which is part of the STS-1 payload is a stuff byte, i.e. no DS3 bits (neither overhead nor payload) are contained therein.
Referring now to FIG. 1 of the above article, the like patterns normally constituting the gapped DS3 clock stream are composed as follows. 32 gaps followed by 688 clock periods into which the sequence: 19 gaps--205 pulses--24 gaps--208 pulses--24 gaps--208 pulses, is mapped, i.e. the latter sequence begins at one of the 688 clock periods and ends at the corresponding clock period of the next pattern.
The last gap of the second series of 24 gaps corresponds to a stuff opportunity bit. Thus, when the control means detects that the above stuff control bits (the control signal) indicate that this stuff opportunity bit contains information then the latter last gap is replaced by a pulse.
When the control means detects that the above H1 and H2 bytes (the control signal) indicate that a pointer movement occurs then either a sequence of 8 gaps is inserted after the above 32 gaps whereafter the sequence of 688 clock periods is continued, or 8 clock periods (pulses or gaps) of the 688 clock periods are substituted for the last 8 gaps of the above 32 gaps.
As a pointer movement would give rise to an unexpected but short variation (increase or decrease) of the rate with which the bits are written in the FIFO, i.e. of the rate of the information bits in the binary input signal, and thereby to a temporary but unacceptable variation of the average rate with which the bits are read from the FIFO, these pointer movements are treated in a second FIFO preceding the above first mentioned FIFO and by means of which they are leaked out over a longer period of time in order to avoid the mentioned unexpected variation. By choosing the FIFO length such that the most significant bits of the read and write addresses are high for half the length of the FIFO, and by comparing the most significant bits of the read and write addresses in the subtracter, a signal is created with a duty cycle proportional to the filling level of the FIFO. This signal is then applied to the low pass filter wherein jitter due to the overhead gapping is filtered out. The oscillator then provides a clock for a counter providing the read address, thus locking the average rate of bits read from the FIFO and corresponding to the read address to the average rate of bits written therein and corresponding to the write address. To be noted that the read address is incremented at a substantially constant rate due to the low pass filter included in the phase locked loop arrangement.